One known example of a conventional nonvolatile semiconductor memory device is a NAND type flash memory. A memory cell array in a NAND type flash memory is configured as an arrangement of a plurality of NAND cell units, each of the NAND cell units having a plurality of memory cells connected in series therein. One NAND cell unit comprises: a memory string configured from the plurality of memory cells connected in series; and select gate transistors connected to both ends of the memory string. A plurality of NAND cell units commonly connected to one word line configures one block which is a smallest unit of an erase operation.
The erase operation in the above-described NAND type flash memory includes an erase pulse application operation for applying an erase pulse to the memory cell, and an erase verify operation for judging whether a certain erase state has been achieved or not. In this erase operation, it is preferable that a threshold voltage distribution indicating the erase state does not shift excessively to a negative side, since such a shift lowers the speed of a write operation next performed. Therefore, a technology for preventing the threshold voltage distribution indicating the erase state from shifting excessively to a negative side is wanted.